3D IC Development Needs Innovative Socket Solution

In a stacked package, typically the bottom package is processor and the top pa of additional applications required by consumer industry, IC engineers add more features to their 2 generation processor and the memory performance is increased by faster communication to the processor. Test engineers need a sock seen many product offerings for this one level stacked socket. In order to move from 1 2 nd generation devices, a test engineer needs engineer needs to use a processor probe in connect with logic analyzer to perform the probe in between the memory and processor (Fig 1) below shows a typical four level interconnect enabling development sequence of 3D ICs Designing a socket to accommodate these variations bring challenges are addressed.